module top_module (
    input clk,
    input resetn,
    input [1:0] byteena,
    input [15:0] d,
    output [15:0] q
);

    // Incorrect
    // always @(posedge clk) begin
    //     if(~resetn) begin
    //         q <= 0;
    //     end
    //     else begin
    //         q[15:8] <= byteena[1] ? d[15:8] : 0;
    //         q[7:0] <= byteena[0] ? d[7:0] : 0;
    //     end
    // end

    always @(posedge clk) begin
        if(~resetn)
           q <= 16'd0;
        else if(byteena[0] || byteena[1]) begin
            if(byteena[1])  
                q[15:8] <= d[15:8];
            if(byteena[0])  
                q[7:0] <= d[7:0];
        end
    end

endmodule
